.EDA设计交通信号灯
时间:2020-11-05 16:47:33 来源:勤学考试网 本文已影响 人
实验四:交通信号灯的设计
实验要求:
1)当东西走向的绿灯亮时,南北走向的红灯亮,并保持3个clock;
2)当东西走向的黄灯亮时,南北走向的红灯亮,并保持1个clock;
3)当东西走向的红灯亮时,南北走向的绿灯亮,并保持3个clock;
4)当东西走向的红灯亮时,南北走向的黄灯亮,并保持1个clock;
实验原理
程序设计
仿真实验
Verilog HDL代码如下:
module traffic (clock,reset,red1,yellow1,yellow2,green1,red2,green2);
inputclock,reset;
output red1,yellow1,green1,red2,yellow2,green2;
parameter st0 = 0,st1 = 1,st2= 2,st3 = 3,st4=4,st5=5,st6=6,st7=7;
reg[2:0]state,nxstate;
reg red1,yellow1,green1,red2,yellow2,green2;
always@(posedge clock or posedge reset)
begin
if(reset)
state<=st0;
else
state<= nxstate;
end
always@(state)
begin
red1<=1'b0;yellow1<=1'b0;green1<= 1'b0;
red2<=1'b0;yellow2<=1'b0;green2<=1'b0;
case(state)
st0:begin
green1<= 1'b1;
red2<=1'b1;
nxstate<= st1;
end
st1:begin
green1<= 1'b1;
red2<=1'b1;
nxstate<= st2;
end
st2:begin
green1<= 1'b1;
red2<=1'b1;
nxstate<= st3;
end
st3:begin
yellow1<= 1'b1;
red2<= 1'b1;
nxstate<=st4;
end
st4:begin
red1<= 1'b1;
green2<= 1'b1;
nxstate<= st5;
end
st5:begin
red1<= 1'b1;
green2<= 1'b1;
nxstate<= st6;
end
st6:begin
red1<= 1'b1;
green2<= 1'b1;
nxstate<= st7;
end
st7:begin
red1<= 1'b1;
yellow2<= 1'b1;
nxstate<= st0;
end
endcase
end
endmodule
建立波形编辑文件进行功能仿真,仿真结果(局部)如下图所示
生成的RTL电路如下
实验总结
从实验要求看出红绿灯转换只有三个状态,但从代码中可以得知,程序中共设置了七个状态,但总的时钟不变,还是8个时钟。实质上就是状态一和状态四的时钟延长至3个,从而满足了实验要求。